Design And Reuse SoC News Alert

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June 6, 2005

WELCOME

Michael,
Welcome to the issue of June 6, 2005 of D&R SoC News Alert, our email update to provide you with the latest news and information in the System-On-Chip Community.

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NEW IP/SOC PRODUCTS

Verification IP for SATA from Denali Software, Inc.

PCI Specification 2.3 bus controller with FIFO from Actel Corp.

APB SPI Lite IP Core from HDL Design House

Video Scaler IP Core from Zoran Corp.

Low power, small area AHB to USB 2.0 OTG Bridge from Innovative Semiconductors

PHEX 16 Lane Endpoint Controller for PCI Express architecture from Cadence Design Systems

SAS SystemC Verification Component from eInfochips, Inc.

BUSINESS OPPORTUNITIES

Wanted IPs :

SLIC (subscriber line interface circuit)

10/100 ethernet PHY

INDUSTRY ARTICLES

Electronic system-level development: Finding the right mix of solutions for the right mix of engineers

Multi-Gigabit SerDes: The Cornerstone of High Speed Serial Interconnects

The Challenge of Keeping IP Usable

COMMENTARY/ANALYSIS

Doors 'open' to hardware

Toshiba: No money in structured Asics

IN THE NEWS

IP/SOC PRODUCTS

Silicon Hive, a semiconductor IP supplier in the Philips Technology Incubator, Demonstrates World's First Fully Programmable Digital TV Demodulator IP Core

ARM Artisan Low Power IP Offered By IBM, Chartered To Support 65-Nanometer Common Platform

Synopsys Enables Rapid Adoption of SATA Interface With DesignWare Verification IP

Xilinx Announces Immediate Availability of Industry's First 4 Gbps Programmable Fibre Channel Solution

Rambus PCI Express PHY Passes Standard Compliance Testing; Silicon-Proven IP Achieves Five Entries on PCI-SIG Integrators List

AccelChip Facilitates Sensor Array Processing with New SVD Matrix Factorization DSP IP Core

HiTech Global Distribution announces Availability of the world's fastest 8051 Microcontroller IP Core with JTAG on-chip debug interface

Actel Broadens Popular PCI Product Family With CorePCIF

DEALS

K-Micro Licenses Virtual Silicon 90nm Mobilize PLL Digital Frequency Synthesizer

LSI Logic Licenses ZSP500 to Renesas Technology for Mobile Applications

Corrent Chooses Faraday's NC-1 for Network Security Processor Chip

IPWireless Standardizes on ARC's Patented Configurable Core Technology for 3G Data Communications Chipset

Transmeta Announces Processor Technology License And Sale Agreement For The Chinese Market

BUSINESS

Heard on the Beat: AMD-ST to merge memory units?

YOGITECH raises one million Euros in early stage venture capital financing from Toscana Venture

Xignal accelerates transition to fabless semiconductor model with appointment of Sean Moynagh as Director of Operations

FINANCIAL RESULTS

Altera Narrows Second Quarter Revenue Guidance

PEOPLE

Chartered Names Dr. Liang Choo Hsia as SVP Technology Development

EMBEDDED SYSTEMS

Xilinx, CorEdge and Yamaichi Demonstrate Flexible 10gbps Packet Processing on Industry Standard ATCA/AMC Platform

Renesas Technology Releases Enhanced aacPlus Decoding Middleware as SH-Mobile Application Processor Software

Feroceon processor reorganizes ARM's pipeline, says In-Stat

FOUNDRIES

UMC Celebrates 25th Anniversary

TSMC, UMC, start pushing out lead times

FPGA/CPLD

Xilinx Announces Customer Shipments Of Virtex-4 FX60 FPGAs With Industry's First 622Mbps - 10.3125Gbps Serial Transceivers

Xilinx Widens Process Technology Leadership - Ships More Than 3.5 Million 90nm FPGAs

Xilinx Virtex-II Pro World's Most Popular 130nm FPGA

Lattice Launches LEADER Design Services Program

Altera's Stratix FPGAs Boost Performance and Drastically Reduce Cost for Cape Range Wireless

FABLESS / IDM

STMicroelectronics Adds DSP to Reconfigurable-Processor SoC for Wireless Infrastructure Applications

Infineon and Nanya Announce Production Readiness of 90nm Technology: Volume Manufacturing of Memory Products Started

EZchip Doubles the Price-Performance of 2.5-Gigabit Network Processors

FSA Finds Funding of Fabless Companies Rises 36% QoQ

EDA

VSI Alliance Releases New Version of Quality IP Metric

The Open SystemC Initiative Announces Availability of the SystemC Transaction-level Modeling Standard with Broad Industry Support

Giga Scale IC Introduces Industry's First IC Economic Analysis Engine

Poseidon Design Systems joins Altera Access Program

Genesys Testware adds efficient automated insertion of embedded test and repair circuits for memory

Memory Characterization Focus on Yield Improvements

Temento Systems announces PSL On Chip Verification (OCV) in new DiaLite Edition & the Release 4.5

Averant Announces AMBA AXI Protocol Checker

Summit Design Expands Its ESL Solution Suite with Vista 1.1 to Deliver Advanced Analysis and Debug for Expert and Novice SystemC Users

Sonics and TransEDA Collaborate to Advance OCP-Based Tool Flows

FS2 Introduces SB NAVIGATOR≥ Trace Tools For Sonics SiliconBackplane SMART Interconnect

S2C delivers breakthrough FPGA-Based ESL Design with TAI IP

Synopsys Advances VCS Solution by Adding Assertion IP Library and Native Testbench Support for SystemVerilog

LogicVision Debuts Easy to Use Nanometer Test Solution for Higher Yield Quality, Lower Cost-of-Test and Faster Time-to-Market

OTHER

Aware Showcases Its StratiPHY Family of DSL Solutions at SuperComm 2005; Highlights include Aware's VDSL2 intellectual property offering - StratiPHY3

ASICS World Services, Atrenta, Celoxica, First Silicon Solutions, and Jeda Technologies Join OCP International Partnership

Meet the DSP Algorithmic Experts at DAC 2005; AccelChip Focuses on DSP Solutions in Booth 1000

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